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| www..com (R) IBM PowerPC(R) 750FX RISC Microprocessor Datasheet (Support for 750FX Design Revision Level DD 2.X) Version: 2.0 Preliminary June 9, 2003 www..com (R) Copyright and Disclaimer (c) Copyright International Business Machines Corporation 2003 All Rights Reserved Printed in the United States of America June 2003 The following are trademarks of International Business Machines Corporation in the United States, or other countries, or both. IBM IBM Logo PowerPC PowerPC Logo PowerPC 750 PowerPC Architecture RISCWatch Other company, product and service names may be trademarks or service marks of others. All information contained in this document is subject to change without notice. The products described in this document are NOT intended for use in applications such as implantation, life support, or other hazardous uses where malfunction could result in death, bodily injury, or catastrophic property damage. The information contained in this document does not affect or change IBM product specifications or warranties. Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. All information contained in this document was obtained in specific environments, and is presented as an illustration. The results obtained in other operating environments may vary. While the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made. Note: This document contains information on products in the sampling and/or initial production phases of development. This information is subject to change without notice. Verify with your IBM field applications engineer that you have the latest version of this document before finalizing a design. THE INFORMATION CONTAINED IN THIS DOCUMENT IS PROVIDED ON AN "AS IS" BASIS. In no event will IBM be liable for damages arising directly or indirectly from any use of the information contained in this document. IBM Microelectronics Division 1580 Route 52, Bldg. 504 Hopewell Junction, NY 12533-6351 The IBM home page can be found at http://www.ibm.com The IBM Microelectronics Division home page can be found at http://www-3.ibm.com/chips/ Title_750FX_DS_DD2.X.fm.2.0 June 9, 2003 Preliminary www..com Preliminary Datasheet DD 2.X PowerPC 750FX RISC Microprocessor 1. General Information .................................................................................................... 3 1.1 Features ............................................................................................................................................ 1.2 Design Level Considerations and Features ...................................................................................... 1.3 Processor Version Register .............................................................................................................. 1.4 Part Number Information ................................................................................................................... 3 5 5 6 2. Overview ...................................................................................................................... 7 2.1 Block Diagram ................................................................................................................................... 7 2.2 General Parameters .......................................................................................................................... 8 3. Electrical and Thermal Characteristics ..................................................................... 9 3.1 DC Electrical Characteristics ............................................................................................................. 9 3.2 Clock AC Specifications .................................................................................................................. 13 3.3 Spread Spectrum Clock Generator (SSCG) ................................................................................... 14 3.5 60x Bus Output AC Specifications .................................................................................................. 17 3.6 Alternate I/O Timing For 3.3V Bus .................................................................................................. 19 3.6.1 IEEE 1149.1 AC Timing Specifications ................................................................................. 20 4. Dimensions and Signal Assignments ..................................................................... 22 4.1 Module Substrate Decoupling Voltage Assignments ...................................................................... 22 4.2 Package .......................................................................................................................................... 22 4.3 Microprocessor Ball Placement ....................................................................................................... 24 5. System Design Information ..................................................................................... 31 5.1 PLL Considerations ......................................................................................................................... 5.1.1 Restrictions and Considerations for PLL Configuration ......................................................... 5.1.1.1 Configuration Restriction on Frequency Transitions ...................................................... 5.1.2 PLL_RNG[0:1] Definitions for Dual PLL Operation ................................................................ 5.1.3 PLL Configuration .................................................................................................................. 5.2 PLL Power Supply Filtering ............................................................................................................. 5.3 Decoupling Recommendations ....................................................................................................... 5.4 Output Buffer DC Impedance .......................................................................................................... 5.4.1 Input-Output Usage ............................................................................................................... 5.5 Level Protection .............................................................................................................................. 5.6 64 or 32-Bit Data Bus Mode ............................................................................................................ 5.7 IIO Voltage Mode Selection ............................................................................................................ 5.8 Thermal Management ..................................................................................................................... 5.8.1 Heat Sink Selection Example ................................................................................................ 5.8.2 Internal Package Conduction ................................................................................................ 5.8.3 Minimum Heat Sink Requirements ........................................................................................ 5.8.4 Heat Sink Mounting ............................................................................................................... 5.8.5 Thermal Assist Unit ............................................................................................................... 5.8.6 Adhesives and Thermal Interface Materials .......................................................................... 5.8.7 Thermal Interface and Adhesive Vendors ............................................................................. 5.8.8 Heat Sink Vendors ................................................................................................................. 31 32 32 32 33 35 39 42 43 48 49 49 49 49 52 53 54 54 55 56 57 Revision Log ................................................................................................................ 59 750FX_DS_DD2.X_V2.02.fm.2.0 June 9, 2003 Page 1 of 63 www..com Datasheet DD 2.X PowerPC 750FX RISC Microprocessor Preliminary Page 2 of 63 750FX_DS_DD2.X_V2.02.fm.2.0 June 9, 2003 www..com . Preliminary DD 2.X PowerPC 750FX RISC Microprocessor 1. General Information The IBM PowerPC(R) 750FX RISC Microprocessor is a 32-bit implementation of the IBM PowerPC family of reduced instruction set computer (RISC) microprocessors. This document contains pertinent physical and electrical characteristics of the IBM PowerPC 750FX RISC Microprocessor Revision DD 2.X Single Chip Modules (SCM). The IBM PowerPC 750FX RISC Microprocessor is also referred to as the 750FX throughout this document. 1.1 Features This section summarizes the features of the 750FX implementation of the PowerPC ArchitectureTM. Major features of the 750FX include the following: * Branch processing unit - Four instructions fetched per clock - One branch processed per cycle (plus resolving two speculations) - Up to one speculative stream in execution, one additional speculative stream in fetch - 512-entry branch history table (BHT) for dynamic prediction - 64-entry, 4-way set associative branch target instruction cache (BTIC) for eliminating branch delay slots * Decode - Register file access - Forwarding control - Partial instruction decode * Load/store unit - One cycle load or store cache access (byte, half-word, word, double-word) - Effective address generation - Hits under miss (one outstanding miss) - Single-cycle misaligned access within double-word boundary - Alignment, zero padding, sign extend for integer register file - Floating-point internal format conversion (alignment, normalization) - Sequencing for load/store multiples and string operations - Store gathering - Cache and TLB instructions - Big and little-endian byte addressing supported - Misaligned little-endian support in hardware * Dispatch unit - Full hardware detection of dependencies (resolved in the execution units) - Dispatch two instructions to six independent units (system, branch, load/store, fixed-point unit 1, fixed-point unit 2, or floating-point) - 4-stage pipeline: fetch, dispatch, execute, and complete - Serialization control (predispatch, postdispatch, execution, serialization) * Fixed-point units - Fixed-point unit 1 (FXU1): multiply, divide, shift, rotate, arithmetic, logical - Fixed-point unit 2 (FXU2): shift, rotate, arithmetic, logical - Single-cycle arithmetic, shift, rotate, logical - Multiply and divide support (multi-cycle) - Early out multiply - Thirty-two 32-bit general purpose registers * Floating-point unit - Support for IEEE-754 standard single and double-precision floating-point arithmetic - Optimized for single-precision multiply/add - Thirty-two, 64-bit floating point registers - Enhanced reciprocal estimates - 3-cycle latency, 1-cycle throughput, single-precision multiply-add - 3-cycle latency, 1-cycle throughput, double-precision add - 4-cycle latency, 2-cycle throughput, double-precision multiply-add - Hardware support for divide - Hardware support for denormalized numbers - Time deterministic non-IEEE mode * System unit - Executes CR logical instructions and miscellaneous system instructions - Special register transfer instructions 1. General Information Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 Page 3 of 63 www..com PowerPC 750FX RISC Microprocessor Preliminary * L1 Cache structure - 32K, 32-byte line, 8-way set associative instruction cache - 32K, 32-byte line, 8-way set associative data cache - Single-cycle cache access - Pseudo-LRU replacement - Copy-back or write-through data cache (on a page per page basis) - Parity on L1 tags and arrays - 3-state (MEI) memory coherency - Hardware support for data coherency - Non-blocking instruction cache (one outstanding miss) - Non-blocking data cache (two outstanding misses) - No snooping of instruction cache * Memory management unit - 64 entry, 2-way set associative instruction TLB (total 128) - 64 entry, 2-way set associative data TLB (total 128) - Hardware reload for TLBs - 8 instruction BATs and 8 data BATs - Virtual memory support for up to 4 exabytes (252) virtual memory - Real memory support for up to 4 gigabytes (232) of physical memory - Support for big/little-endian addressing * Dual PLLs - Allows seamless frequency switching * Level 2 (L2) cache - Internal L2 cache controller and 4K-entry tags: 512KB data SRAMs - Two-way set-associative, supports locking by way - Copy-back or write-through data cache on a page basis, or for all L2 - 64-byte sectored line size - L2 frequency at core speed - ECC protection on SRAM array - Parity on L2 tags - Supports up to 2 outstanding misses (1 data and 1 instruction or 2 data) * Power - Low power consumption with low voltage application at lower frequency - Dynamic power management - 3 static power save modes (doze, nap, and sleep) - Thermal Assist Unit (TAU) * Bus interface - 32-bit address bus - 64-bit data bus (also supports 32-bit mode) - Enhanced 60x bus: pipelines consecutive reads to a depth of 2 - Core-to-bus frequency multipliers of 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x, 8x, 8.5x, 9x, 9.5x, 10x, 11x, 12x, 13x, 14x, 15x, 16x, 17x, 18x, 19x, and 20x supported - Supports 1.8V, 2.5V, or 3.3V I/O modes * Reliability and serviceability - Parity checking on 60x interface - ECC checking on L2 cache - Parity on the L1 arrays - Parity on the L1 and L2 tags * Testability - LSSD scan design - Powerful diagnostic and test interface through Common On-Chip Processor (COP) and IEEE 1149.1 (JTAG) interface Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 1. General Information Page 4 of 63 www..com Preliminary DD 2.X PowerPC 750FX RISC Microprocessor 1.2 Design Level Considerations and Features The 750FX supports several unique features including those listed below. The IBM application note Differences between the PowerPC 750FX, 750, 750CX, and 750CXe Microprocessors provides a more detailed explanation of these features. * Incorporates an on-chip, 512K, two-way, set-associative L2 cache * Provides a 64 or 32-bit Data Bus mode (per setup of TLBISYNC pin) * Supports 1.8V, 2.5V, or 3.3V I/O modes Implementation Note: DD2.0 supports a limited use of the 3.3V I/O mode. For additional information, see the 750FX Errata List of Revision DD2.X. * Includes all 60x bus pins on earlier PowerPC 750 designs and additional signals * Enhanced 60x bus -- for pipelined consecutive read transactions and higher frequency operation * Dual PLLs for additional power savings capabilities * Four additional IBAT/DBAT registers * New CBGA package with additional pins and depopulated footprint 1.3 Processor Version Register The PowerPC 750FX RISC Microprocessor has the following Processor Version Register (PVR) values for the respective design revision levels. The 750FX PVR is 7000, which is not used in any previous PowerPC processor design. Table 1-1. 750FX Processor Version Register (PVR) 750FX Design Revision Level DD2.0 DD2.1 DD2.2 DD2.3 Note: 1. Nibbles shown as `b' are to be ignored, and are for factory use only. Nibbles shown as `a' may be 0 or 1 2. If L2_TSTCLK is pulled low, the PVR may read 0x000802b_. L2TSTCLK should be pulled up for normal operation. 750FX PVR 0x700a02b0 0x700a02b1 0x700a02b2 0x700a02b3 Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 1. General Information Page 5 of 63 www..com DD 2.X PowerPC 750FX RISC Microprocessor Preliminary 1.4 Part Number Information Figure 1-1. Part Number Legend IBM25PPC750FX-GByy x3T PowerPC 750 Family Member Process Technology Design Revision Level Package Type Shipping Container Reliability Grade Test Conditions Performance Sort Process Technology Design Revision Level "--" = 0.13 m CSOI D = DD2.0 E = DD2.1 F = DD2.2 G = DD2.3 B = Ceramic Ball Grid Array 01 = Nominal at 600 MHz 05 = Nominal at 700 MHz 10 = Nominal at 733 MHz 25 = Nominal at 800 MHz 1 = (see Datasheet Supplement and PCN-IBM-050803 2 = Special Test Conditions 3 = 1.4 - 1.5V @ 105C 3 = Grade 3, <100 FIT AFR 2 = Grade 2, < 25 FIT AFR T = Tray Package Type Performance Sort Test Conditions Reliability Grade Shipping Container Note: See the Datasheet Supplement for additional application conditions. 1. General Information Page 6 of 63 Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 www..com Preliminary DD 2.X PowerPC 750FX RISC Microprocessor 2. Overview The PowerPC 750FX RISC Microprocessor, also called the 750FX, is targeted for high performance, low power systems using a 60x bus. The 750FX also includes an internal 512KB L2 cache with on-board Error Correction Circuitry (ECC). 2.1 Block Diagram Figure 2-1 shows a block diagram of the PowerPC 750FX RISC Microprocessor. Figure 2-1. PowerPC 750FX RISC Microprocessor Block Diagram Control Unit Completion Instruction Fetch Branch Unit 32KB I-Cache with Parity System Unit Dispatch BHT / BTIC GPRs FPRs LSU FPU Rename Buffers FXU1 FXU2 Rename Buffers 512KB 32KB D-Cache with parity L2 Tags with parity L2 Cache w/ECC Enhanced 60x BIU Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 2. Overview Page 7 of 63 www..com DD 2.X PowerPC 750FX RISC Microprocessor Preliminary 2.2 General Parameters Table 2-1 provides a summary of the general parameters of the 750FX. Table 2-1. 750FX General Parameters Item Technology Die Size Transistor count Logic design Package Core power supply I/O power supply Note: 1. In some cases, when using 1.8v or 2.5v IO mode, it is possible to reduce power dissipation by lowering the core power supply voltage. See the Datasheet Supplement for details. 2. BVSEL =0, L1_TSTCLK = 0 is an INVALID setting. DD2.0 supports only a limited use of 3.3v IO mode. See the 750FX Errata List for revision DD2.x for more information. Description 0.13m CSOI technology, six-layer metallization plus one level of local interconnect 34.3 sq. mm 38 million - including L2 cache Fully-static 292-pin ceramic ball grid array (CBGA) 21x21mm (1.0 mm pitch) 0.8 mm ball size 1.45V +/- 50 mV 3.3V +/- 165mV (BVSEL = 1, L1_TSTCLK = 0) or 2.5V +/- 125mV (BVSEL = 1, L1_TSTCLK = 1) or 1.8V +/- 100mV (BVSEL = 0, L1_TSTCLK = 1) 1 2 Notes 2. Overview Page 8 of 63 Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 www..com Preliminary DD 2.X PowerPC 750FX RISC Microprocessor 3. Electrical and Thermal Characteristics This section provides AC and DC electrical specifications and thermal characteristics for the 750FX. 3.1 DC Electrical Characteristics The tables in this section describe the DC electrical characteristics for the 750FX. Table 3-1. Absolute Maximum Ratings1 Characteristic Core supply voltage PLL supply voltage 60x bus supply voltage Input voltage Storage temperature range Notes: 1. Functional and tested operating conditions are given in Table 3-2, "Recommended Operating Conditions" on page 10. Absolute maximum ratings are stress ratings only, and functional operation at the maximums is not guaranteed. Stresses beyond those listed above may affect device reliability or cause permanent damage to the device. 2. Caution: Transient VIN overshoots of up to OVDD + 0.8V, with a maximum of 4.0V for 3.3V operation, and undershoots down to GND - 0.8V, are allowed for up to 5ns. 3. Caution: OVDD must not exceed VDD/AVDD by more than 2.1V continuously. OVDD may exceed VDD/AVDD by up to 2.3V for up to 20ms during power-on or power-off. OVDD must not exceed VDD/AVDD by more than 2.3V for any amount of time. 4. Caution: VDD/AVDD must not exceed OVDD by more than 1.0V continuously. VDD/AVDD may exceed OVDD by up to 1.6v for up to 20ms during power-on or power-off. VDD/AVDD must not exceed OVDD by more than 1.6V for any amount of time. 5. Caution: AVDD must not exceed VDD by more than 0.5V at any time. Symbol VDD A1VDD, A2VDD OVDD VIN TSTG 1.8V -0.3 to 1.6 -0.3 to 1.6 -0.3 to 2.0 -0.3 to 2.0 -55 to 150 2.5V -0.3 to 1.6 -0.3 to 1.6 -0.3 to 2.75 -0.3 to 2.75 -55 to 150 3.3V -0.3 to 1.6 -0.3 to 1.6 -0.3 to 3.7 -0.3 to 3.7 -55 to 150 Unit V V V V C Notes 3, 4 3, 4, 5 3, 4 2 Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 3. Electrical and Thermal Characteristics Page 9 of 63 www..com DD 2.X PowerPC 750FX RISC Microprocessor Preliminary Note: All electrical specifications (AC, DC, timing) are guaranteed only while the device is operated within the recommended operating conditions (see Table 3-2). Operation at other application conditions may also be possible; see the PowerPC 750FX RISC Microprocessor Datasheet Supplement for details. Table 3-2. Recommended Operating Conditions Characteristic Core supply voltage (full-on mode) Low Voltage (Low Frequency Operation, 1.8V and 2.5V bus modes only) PLL supply voltage 60x bus supply voltage (1.8V) 60x bus supply voltage (2.5V) 60x bus supply voltage (3.3V) Input voltage Die-junction temperature DD2.0 and 2.1 Die-junction temperature DD2.2 and 2.3 Notes: 1. In some cases, when using 1.8v or 2.5v IO mode, it is possible to reduce power dissipation by lowering the core power supply voltage. See the Datasheet Supplement for details. 2. These are tested operating conditions. Symbol VDD VDD AVDD OVDD OVDD OVDD VIN TJ TJ Value 1.4 to 1.5 1.2 Minimum 1.4 to 1.5 1.7 to 1.9 2.375 to 2.625 3.135 to 3.465 GND to OVDD 0 to 105 -40 to 105 Unit V V V V V V V C 2 Notes 1, 2 1 2 2 2 Table 3-3. Package Thermal Characteristics1 Characteristic CBGA package thermal resistance, junction-to-case thermal resistance (typical) CBGA package thermal resistance, junction-to-lead thermal resistance (typical) Notes: 1. A heat sink is required (see Section 5.8 Thermal Management on page 49). 2. JC is the internal resistance from the junction to the back of the die. For more information about thermal management, see Section 5.8 Thermal Management on page 49. Symbol2 JC JB Value 0.06 7.6 Unit C/W C/W 3. Electrical and Thermal Characteristics Page 10 of 63 Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 www..com Preliminary DD 2.X PowerPC 750FX RISC Microprocessor Table 3-4. DC Electrical Specifications See Table 3-2 on page 10 for recommended operating conditions. Voltage Characteristic Symbol Min VIH (1.8V) Input high voltage (all inputs except SYSCLK) VIH(2.5V) VIH(3.3V) VIL(1.8V) Input low voltage (all inputs except SYSCLK) VIL(2.5V) VIL(3.3V) CVIH(1.8V) SYSCLK input high voltage CVIH(2.5V) CVIH(3.3V) SYSCLK input low voltage Input leakage current, VIN = applies to all OVDD levels Hi-Z (off state) leakage current, VIN = applies to all OVDD levels CVIL(1.8V) IIN ITSI VOH(1.8V) Output high voltage, IOH = -4mA VOH(2.5V) VOH(3.3V) Output low voltage, IOL = 4mA Capacitance, VIN =0 V, f = 1MHz Notes: 1. Capacitance values are guaranteed by design and characterization, and are not tested. 2. Additional input current may be attributed to the Level Protection Keeper Lock circuitry. For details, see Section 5.5 Level Protection on page 48. Unit Max V V V 0.60 0.70 0.80 1.20 1.90 2.1 0.40 20 20 1.30 2.00 2.40 0.4 5 V V V V V V V A A V V V V pF 1.20 1.70 2.1 Notes 2 2 VOL(1.8V, 2.5V, 3.3V) CIN 1 Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 3. Electrical and Thermal Characteristics Page 11 of 63 www..com DD 2.X PowerPC 750FX RISC Microprocessor Preliminary Table 3-5. Power Consumption See Table 3-2 on page 10 for recommended operating conditions. Representative Processor Frequency (see note 6) Mode Full-On Mode 1.45V Maximum 1.5V Typical Nap Mode Typical Sleep Mode Typical Notes: 1. These values apply for all valid 60x buses. The values do not include I/O Supply Power (OVDD) or PLL/DLL supply power (AVDD). OVDD power is system dependent, but is typically <2% of VDD power. AVDD current is less than 25mA each for AVDD1 and AVDD2. 2. Maximum power is specified for fastest (worst process) parts running RC5 at the indicated core voltage, junction temperature, and core frequency. 3. Typical power is specified for median process 800 MHz parts0 running RC5 at the indicated core voltage, junction temperature, and core frequency. The value is then adjusted for 13% less switching (AC component for PD) to account for the differences between RC5 and more typical application code. VDD Tj Unit 400 MHz 600 MHz 700 MHz 733 MHz 800 MHz Notes 105C 105C 85C 7.1 7.9 3.9 7.9 8.7 4.6 8.2 9.3 5.0 8.3 9.4 5.1 8.6 9.7 5.4 1, 2 1, 2 1, 3 1.45V 1.45V 50C 1.4 1.5 1.6 1.6 1.6 W 1 1.45V 50C 1.4 1.4 1.4 1.4 1.4 W 1 Previous revisions of this datasheet showed incorrectly low power dissipation values. The power dissipation of the 750FX has not increased, the datasheet has only been corrected to show the actual values. 3. Electrical and Thermal Characteristics Page 12 of 63 Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 www..com Preliminary DD 2.X PowerPC 750FX RISC Microprocessor 3.2 Clock AC Specifications Table 3-6 provides the clock AC timing specifications as defined in Figure 3-1. Table 3-6. Clock AC Timing Specifications (See Table 3-2 on page 10 for recommended operating conditions1,6) Num (Timing Reference) Processor frequency SYSCLK frequency 1 2, 3 4 VMSYSCLK SYSCLK cycle time SYSCLK rise and fall slew rate SYSCLK duty cycle measured at 0.8V Measurement Reference Voltage for SYSCLK (all I/O voltages) SYSCLK cycle-to-cycle jitter Internal PLL relock time Notes: 1. Caution: The SYSCLK frequency and the PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK (bus) frequency, CPU (core) frequency, and PLL frequency do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0:4] signal description in Table 5-2, "750FX Microprocessor PLL Configuration" on page 33 for valid PLL_CFG[0:4] settings. 2. The SYSCLK slew rate applies between 0.4V and 1.0V. 3. Timing is guaranteed by design and characterization, and is not tested. 4. See Section 3.3 Spread Spectrum Clock Generator (SSCG) on page 14 for long term jitter. 5. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the maximum amount of time required for PLL lock after a stable VDD and SYSCLK are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence. 6. This is a statement of the capability of the 750FX I/O circuitry. Not all systems can run at the maximum SYSCLK frequency. Contact IBM PowerPC Application Engineering for more information on high-speed bus design. 7. Lower voltage/frequency operation: For additional information, see 750FX Datasheet Supplement for DD2.X Revisions. - - Value Characteristic Min. 400 20 5.0 1.0 25 0.65 150 100 Max. 800 200 50 -- 75 MHz MHz ns V/ns % V ps s 4, 3 5 3 3 7 1, 6 Unit Notes Figure 3-1. SYSCLK Input Timing Diagram 1 2 4 4 CVIH VM SYSCLK CVIL VMSYSCLK - Midpoint Voltage for SYSCLK 3 Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 3. Electrical and Thermal Characteristics Page 13 of 63 www..com DD 2.X PowerPC 750FX RISC Microprocessor Preliminary 3.3 Spread Spectrum Clock Generator (SSCG) When designing with the SSCG, there are a number of design issues that must be taken into account. SSCG creates a controlled amount of long-term jitter. In order for a receiving PLL in the 750FX to operate in this environment, it must be able to accurately track the SSCG clock jitter. The accuracy to which the 750FX PLL can track the SSCG clock is referred to as tracking skew. When performing system timing analysis, the tracking skew must be added or subtracted to the I/O timing specifications because the tracking skew appears as a static phase error between the internal PLL and the SSCG clock. To minimize the impact on I/O timings the following SSCG configuration is recommended: The following SSCG configuration is recommended: * - Down spread mode, less than or equal to 1% of the maximum frequency * - A modulation frequency of 30kHz * - Linear sweep modulation or "Hershey Kiss1" (as in a Lexmark2 profile) modulation profile as shown in Figure 3-2 on page 14. In this configuration the tracking skew is less than 100ps. Figure 3-2. Linear Sweep Modulation Profile 0% Percentage Decreases Down spread frequency change -1% 0s Time Increases 33.3s 1. Hershey Kiss is a trademark of Hershey Foods Corporation. 2. See patent 5,631,920. 3. Electrical and Thermal Characteristics Page 14 of 63 Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 www..com Preliminary DD 2.X PowerPC 750FX RISC Microprocessor 3.4 60x Bus Input AC Specifications Table 3-7. 60x Bus Input Timing Specifications See Table 3-2 on page 10 for operating conditions.1,5 Num Characteristic 1.8V Mode Min. 1.0 1.5 8 0.65 1.5 0 -- -- -- Max. -- 2.5V Mode Min. 1.5 1.5 8 0.65 2.5 0 -- -- -- Max. 3.3V Mode Min. 1.8 1.8 8 0.55 2.5 0 -- -- -- tSYSCLK 2, 3, 4, 5 ns ns ns -- 2, 4, 5 -- 6 Max. -- Unit ns Notes -- 10a All inputs valid to SYSCLK (input setup) 10b 10c INT_, SMI_, MCP, TBEN, DRTRY, and TLBISYNC (input setup) Mode select input setup to HRESET (TLBISYNC, DRTRY) 11a SYSCLK to inputs invalid (input hold) 11b 11c VM Notes: INT_, SMI_, MCP, TBEN, DRTRY, and TLBISYNC (input hold) HRESET to mode select input hold (TLBISYNC, DRTRY) Measurement Reference Voltage for Inputs OVDD/2 1. Input specifications are measured from the VM of the signal in question to VM of the rising edge of the input SYSCLK. Input and output timings are measured at the pin (see Figure 3-3). 2. The setup and hold time is with respect to the rising edge of HRESET (see Figure 3-4 on page 16). 3. tSYSCLK, is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration (in ns) of the parameter in question. 4. This specification is for configuration mode select only. Also note that the HRESET must be held asserted for a minimum of 255 bus clocks after the PLL relock time during the power-on reset sequence. 5. All values are guaranteed by design, and are not tested. 6. See Alternate I/O Timing For 3.3V Bus on page 19 Figure 3-3 provides the input timing diagram for the 750FX. Figure 3-3. Input Timing Diagram VMsysclk(0.65V) SYSCLK 10a 10b 11a 11b ALL INPUTS VM VM VM = Midpoint Voltage (OVDD/2) Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 3. Electrical and Thermal Characteristics Page 15 of 63 www..com DD 2.X PowerPC 750FX RISC Microprocessor Preliminary Figure 3-4 provides the mode select input timing diagram for the 750FX. Figure 3-4. Mode Select Input Timing Diagram VIH HRESET 10c 11c 10c 11c MODE PINS VIH = 1.20V for 1.8V OVDD VIH = 1.70V for 2.5V OVDD VIH = 2.1V for 3.3V OVDD 3. Electrical and Thermal Characteristics Page 16 of 63 Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 www..com Preliminary DD 2.X PowerPC 750FX RISC Microprocessor 3.5 60x Bus Output AC Specifications Table 3-8 provides the 60x bus output AC timing specifications for the 750FX as defined in Figure 3-6 on page 19. Table 3-8. 60x Bus Output AC Timing Specifications See Table 3-2 on page 10 for operating conditions.1, 5 Num Characteristic Min. 12 13 14 15 16 17 SYSCLK to Output Driven (Output Enable Time) SYSCLK to Output Valid SYSCLK to Output Invalid (Output Hold) SYSCLK to Output High Impedance (all signals except ARTRY, ABB and DBB) SYSCLK to ABB and DBB high impedance after precharge SYSCLK to ARTRY high impedance before precharge SYSCLK to ARTRY precharge enable Maximum delay to ARTRY precharge SYSCLK to ARTRY high impedance after precharge 0.3 -- 0.5 -- -- -- 0.2x tSYSCLK + 1.0 -- -- 1.0 2.0 Max. -- 2.3 -- 2.5 1.0 3.0 Min. 0.3 -- 0.55 -- -- -- 0.2x tSYSCLK + 1.0 -- Max. -- 2.5 -- 2.5 1.0 3.0 Min. 0.3 -- 0.55 -- -- -- 0.2x tSYSCLK + 1.0 -- Max. -- 2.5 - 2.5 1.0 3.0 ns ns ns ns tSYSCLK ns -- 2, 6 2, 7 -- 3, 4 -- 1.8V 2.5V 3.3V Unit Notes 18 19 20 Notes: -- 1.0 2.0 -- 1.0 2.0 ns tSYSCLK tSYSCLK 2, 3, 4 3, 4 3, 4 1. All output specifications are measured from the VM of the rising edge of SYSCLK to the output signal level defined in Figure 3-5 on page 18. Both input and output timings are measured at the pin. Timings are determined by design. 2. This minimum parameter assumes CL = 0pF. 3. tSYSCLK is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period of SYSCLK to compute the actual time duration of the parameter in question. 4. Nominal precharge width for ARTRY is 1.0 tSYSCLK. 5. Guaranteed by design and characterization, and not tested. 6. Output Valid timing increases as the VDD in reduced. These values assumes VDD minimum of 1.35V. 7. See Alternate I/O Timing For 3.3V Bus on page 19 Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 3. Electrical and Thermal Characteristics Page 17 of 63 www..com DD 2.X PowerPC 750FX RISC Microprocessor Preliminary Figure 3-5. Output Valid Timing Definition Output Driver 65 ohm line SYSCLK Positive Output Transition VM Negative Output Transition 1/4 OVDD 3/4 OVDD Output Transition defined between SYSCLK @ VM and the respective transition level. Note: The timing definition uses an infinitely long transmission line model. 3. Electrical and Thermal Characteristics Page 18 of 63 Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 www..com Preliminary DD 2.X PowerPC 750FX RISC Microprocessor Figure 3-6. Output Timing Diagram for PowerPC 750FX RISC Microprocessor VMSYSCLK VMSYSCLK VMSYSCLK SYSCLK 13 14 All Outputs (Except TS, ARTRY) 12 VM 15 VM 13 13 14 15 TS VM 16 ABB, DBB 20 19 18 ARTRY 17 High Level Low Level Hi-Z Note: SYSCLK VM as defined in Section 3.2 Clock AC Specifications on page 13. Output VM as defined in Section 3-5 Output Valid Timing Definition on page 18. 3.6 Alternate I/O Timing For 3.3V Bus An alternate I/O timing specification may be used for dd2.3, where: * OVDD = 3.3V +/- 5%, * VDD = 1.45V +/- 50mV, and * Tj = -400 C to 1050 C. * All other recommended operating conditions are as per Table 3-2. The following alternate I/O timing specifications may be used under the above conditions: 1. Consider VM = 1/2 (OVDD) for SYSCLK, input timing, and output timings. 2. Input hold (T11a) becomes 250 ns minimum for 3.3V. Output hold (T14) becomes 650 ns minimum for 3.3V. 3. All other timing specifications are unchanged. Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 3. Electrical and Thermal Characteristics Page 19 of 63 www..com DD 2.X PowerPC 750FX RISC Microprocessor Preliminary 3.6.1 IEEE 1149.1 AC Timing Specifications The five JTAG signals are; TDI, TDO, TMS, TCK, and TRST. Unless otherwise noted, JTAG specifications are referenced to GND and OVDD. The JTAG I/Os are powered by OVDD. Table 3-9. JTAG AC Timing Specifications (Independent of SYSCLK) See Table 3-2 on page 10 for operating conditions. Num Characteristic TCK frequency of operation 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Notes: 1. 2. 3. 4. 5. TRST is an asynchronous level sensitive signal. Guaranteed by design. Non-JTAG signal input timing with respect to TCK. Non-JTAG signal output timing with respect to TCK. Guaranteed by characterization and not tested. Minimum specification guaranteed by characterization and not tested. TCK cycle time TCK clock pulse width measured at 1.1V TCK rise and fall times Specification obsolete, intentionally omitted TRST assert time Boundary-scan input data setup time Boundary-scan input data hold time TCK to output data valid TCK to output high impedance TMS, TDI data setup time TMS, TDI data hold time TCK to TDO data valid TCK to TDO high impedance TCK to output data invalid (output hold) 25 0 13 - 3 0 15 2.0 3 0 -- -- -- 8 19 -- -- 12 9 - ns ns ns ns ns ns ns ns ns ns 5 4 1 2 2 3, 5 3, 4 Min. 0 40 15 0 Max. 25 -- -- 2 Unit MHz ns ns ns 4 Notes Figure 3-7. JTAG Clock Input Timing Diagram 1 2 2 TCK 3 VM 3 VM VM VM = Midpoint Voltage (OVDD/2) 3. Electrical and Thermal Characteristics Page 20 of 63 Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 www..com Preliminary DD 2.X PowerPC 750FX RISC Microprocessor Figure 3-8. TRST Timing Diagram TRST 5 Figure 3-9. Boundary-Scan Timing Diagram TCK 6 Data Inputs 8 Data Outputs 9 Data Outputs Input Data Valid 7 Output Data Valid Figure 3-10. Test Access Port Timing Diagram TCK 10 TDI, TMS 12 TDO 13 TDO 11 Input Data (Valid) Output Data (Valid) TDO 14 Output Data (Invalid) Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 3. Electrical and Thermal Characteristics Page 21 of 63 www..com DD 2.X PowerPC 750FX RISC Microprocessor Preliminary 4. Dimensions and Signal Assignments IBM offers a ceramic ball grid array (CBGA) which supports 292 balls for the 750FX package. 4.1 Module Substrate Decoupling Voltage Assignments The on-board substrate voltage-to-ground assignments for the capacitor locations are shown in Figure 4-1. Figure 4-1. Module Substrate Decoupling Voltage Assignments 47P6892 GND OVDD VDD GND OVDD GND GND VDD OVDD GND OVDD VDD GND GND A01 Corner 4.2 Package Module mass is approximately 3.25 grams. Ball pitch is 1 mm. Ball diameter target is 0.8 mm +/- 0.04 mm. JEDEC moisture sensitivity level is 1. For pad, line, via, and dogbone recommendations, ask for "Printed Wiring Board Tech For 1.0 mm Pitch Modules." Note: Use A01 corner designation for correct placement. Use the five plated dots that form a right angle (|_) to locate the A01 corner as shown in Figure 4-2 Mechanical Dimensions and Bottom Surface Nomenclature of the CBGA Package on page 23. 4. Dimensions and Signal Assignments Page 22 of 63 Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 www..com Preliminary DD 2.X PowerPC 750FX RISC Microprocessor Figure 4-2. Mechanical Dimensions and Bottom Surface Nomenclature of the CBGA Package B1 B Notes: 4. Dimensioning and tolerancing per ASME Y14.5M, 1994. 5. Dimensions in millimeters. Millimeters DIM A Minimum 7.03 1.5 21 0.2 5.32 1.5 0.48 0.51 2.5 2.569 1.859 0.779 (7x) 0.20 1.79 1.08 0.71 3.087 2.177 0.857 0.51 2.23 1.32 0.91 Maximum 47P6892 21 0.2 A2 A1 A2 B B1 C A1 A C1 C2 D F F1 G G1 H H1 H2 A01 Corner YWVUTRPNMLK JHGFEDCBA 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 (19X) 1 3 2 1 F C1 F1 D C2 C H1 (19X) 1 292X (bottom side view) G1 A01 Corner H2 H Not To Scale b 0.3 C A B 0.1 C G Note: All caps on the SCM are lower in height than the processor die. Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 4. Dimensions and Signal Assignments Page 23 of 63 www..com DD 2.X PowerPC 750FX RISC Microprocessor Preliminary 4.3 Microprocessor Ball Placement Figure 4-3. PowerPC 750FX Microprocessor Ball Placement 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A6 A13 A11 A12 A14 TT3 TSIZ0 A8 GND A10 A3 A5 A2 A4 A0 A1 DH31 DH25 DH26 DH29 DP3 DP2 DH22 DH19 DH18 DH16 DH15 DH14 DP1 DH17 DH11 DP0 DH8 GND DH1 DH7 DH9 DH6 OVDD DH10 DH5 DH4 GND DH0 DH2 DH3 PLL_CFG0 PLL_CFG2 A2VDD A1VDD AGND DH28 DH23 DH24 DH21 DH20 VDD VDD GND GND OVDD OVDD OVDD GND A9 AP0 A7 VDD GND VDD VDD OVDD GND DH30 DH27 GND OVDD GND OVDD DH12 DH13 OVDD GND VDD TT1 OVDD A15 TS TT2 OVDD TT0 GND OVDD PLL_CFG1 PLL_CFG3 GND SYSCLK PLL_RNG0 OVDD GND GND OVDD GND VDD VDD GND OVDD GND OVDD PLL_RNG1 OVDD PLL_CFG4 LLSD_ MODE AP2 TT4 GND AP1 GND GND VDD VDD VDD VDD GND GND GND L2_TSTCLK L1_TSTCLK TA TBST DBDIS A18 AACK A20 DBWO TSIZ1 GND GND VDD VDD GND GND GND VDD GND GND MCP GND GND VDD TLBISYNC VDD SMI BVSEL VDD GND QREQ DBB GND OVDD TBEN ARTRY TEA CLK_O UT CI GND TCK DL31 OVDD DL30 TRST TDI TMS CHECKSTOP HRESET CKSTP INT QACK SRESET ABB TSIZ2 VDD GND OVDD GND A16 A17 AP3 GND A21 VDD GND VDD GND OVDD VDD GND OVDD GND VDD VDD GND VDD GND GND VDD VDD VDD VDD GND GND OVDD GND GND OVDD VDD OVDD OVDD OVDD GND A19 OVDD A24 A23 A22 A26 GND A25 A31 WT GND OVDD TDO DBG A28 A29 DL0 DL1 A27 OVDD A30 GND DP4 DL2 DL4 DL3 OVDD GND DL6 DL8 DL5 DL7 DP5 DL13 GND GND VDD VDD DL23 DL26 GND OVDD BG DRTRY GND GBL RSRV BR BLANK BLANK OVDD GND DL11 DL10 DL12 DL16 DL15 DL19 DL20 DL22 DL27 DL28 DL9 DL14 DP6 DL18 DL17 DL21 DP7 DL24 DL25 DL29 A B C D E F G H J K L M N P R T U V W Y Note: This view is looking down from above the 750FX placed and soldered on the system board. 4. Dimensions and Signal Assignments Page 24 of 63 Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 www..com Preliminary DD 2.X PowerPC 750FX RISC Microprocessor 4.4 Pinout Listings Table 4-1 contains the pinout listing for the 750FX CBGA package. Table 4-1. Pinout Listing for the CBGA package Signal Name A[0:31] A1VDD A2VDD AACK ABB AGND AP[0:3] ARTRY BG BLANK BR BVSEL CHECKSTOP (CKSTP_OUT) CI CKSTP_IN CLK_OUT DBB DBDIS DBG DBWO Pin Number E20, E19, D20, C20, D19, C19, A20, E16, B20, E17, B18, A18, A17, A19, A16, B16, B10, B9, A9, B7, A7, D8, A5, B6, D7, D5, B5, B4, A4, A3, B3, E5. Y15 Y16 A8 Y6 Y14 D16, D13, A13, B8 W7 W4 Y1, Y2 Y3 W9 Y12 T4 Y10 T5 U7 A10 Y5 A6 W18, T17, Y20, Y19, W20, V19, U19, T16, T19, U20, V20, R19, N17, P17, R20, P20, N20, P19, M20, L20, M19, L19, K20, J19, K19, G20, H20, H17, H19, F19, G17, F20 A2, A1, C2, E4, C1, E2, D2, E1, D1, F1, G2, F2, H2, H4, G1, K2, J2, K1, J1, L2, M2, L1, N2, N4, N1, P1, P4, P2, R2, R1, U2, T1 T20, N19, J20, G19, B1, G4, H1, M1 W3 W1 Active High -- -- Low Low -- High Low Low -- Low -- Low Low Low High Low Low Low Low Input/Output Input/Output -- -- Input Input/Output -- Input/Output Input/Output Input -- Output Input Output Output Input Output Input/Output Input Input Input 4 3 6 Notes DH[0:31] High Input/Output DL[0:31] DP[0:7] DRTRY GBL Notes: 1. 2. 3. 4. 5. 6. High High Low Low Input/Output Input/Output Input Input/Output 6 These are test signals for factory use only and must be pulled up to OVDD for normal machine operation. OVDD inputs supply power to the Input/Output drivers and VDD inputs supply power to the processor core. These pins are reserved for potential future use. BVSEL and L1_TSTCLK select the Input/Output voltage mode on the 60x bus (see Section 5.7 on page 49). TCK must be tied high or low for normal machine operation. Address and data parity should be left floating if unused in the design. Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 4. Dimensions and Signal Assignments Page 25 of 63 www..com DD 2.X PowerPC 750FX RISC Microprocessor Preliminary Table 4-1. Pinout Listing for the CBGA package (Continued) Signal Name Pin Number B2, B19, C5, C8, C13, C16, D10, D11, E3, E7, E14, E18, F10, F11, G5, G8, G13, G16, H3, H8, H9, H12, H13, H18, J12, K4, K7, K10, K14, K17, L4, L7, L10, L14, L17, M12, N3, N8, N9, N12, N13, N18, P5, P8. P13, P16, R10, R11, T3, T7, T14, T18, U10, U11, V5, V8, V13,V16, W2, W19, Y11 Y9 Y13 W13 U13 W12 C4, C7, C14, C17, D3, D18, E10, E11, G3, G7, G14, G18, H5, H16, K5, K16, L5, L16, N5, N16, P3, P7, P14, P18, T10, T11, U3, U18, V4, V7, V14, V17 Y18, W17, Y17, U16, W14 W15, U14 Y8 U8 Y4 W10 Y7 W16 A12 W8 A11 T2 V2 W5 W6 W11 V1 U1 B15 Active Input/Output Notes GND -- -- HRESET INT L1_TSTCLK L2_TSTCLK LSSD_MODE MCP OVDD PLL_CFG[0:4] PLL_RNG[0:1] QACK QREQ RSRV SMI SRESET SYSCLK TA TBEN TBST TCK TDI TDO TEA TLBISYNC TMS TRST TS Notes: 1. 2. 3. 4. 5. 6. Low Low High High See note 1. Low Low -- High High Low Low Low Low Low High Low High Low High High High Low Low High Low Low Input Input Input Input Input Input -- Input Input Input Output Output Input Input Input Input Input Input/Output Input Input Output Input Input Input Input Input/Output 5 2 4 1 1 These are test signals for factory use only and must be pulled up to OVDD for normal machine operation. OVDD inputs supply power to the Input/Output drivers and VDD inputs supply power to the processor core. These pins are reserved for potential future use. BVSEL and L1_TSTCLK select the Input/Output voltage mode on the 60x bus (see Section 5.7 on page 49). TCK must be tied high or low for normal machine operation. Address and data parity should be left floating if unused in the design. 4. Dimensions and Signal Assignments Page 26 of 63 Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 www..com Preliminary DD 2.X PowerPC 750FX RISC Microprocessor Table 4-1. Pinout Listing for the CBGA package (Continued) Signal Name TSIZ[0:2] TT[0:4] VDD WT Notes: 1. 2. 3. 4. 5. 6. These are test signals for factory use only and must be pulled up to OVDD for normal machine operation. OVDD inputs supply power to the Input/Output drivers and VDD inputs supply power to the processor core. These pins are reserved for potential future use. BVSEL and L1_TSTCLK select the Input/Output voltage mode on the 60x bus (see Section 5.7 on page 49). TCK must be tied high or low for normal machine operation. Address and data parity should be left floating if unused in the design. Pin Number A14, B12, B11 D14, B17, B14, A15, B13 C10, C11, E8, E13, F6, F9, F12, F15, J8, J9, J13, K3, K8, K11, K13, K18, L3, L8, L11, L13, L18, M8, M9, M13, R6, R9, R12, R15, T8, T13, V10, V11 U5 Active High High -- Low Input/Output Output Input/Output -- Output 2 Notes Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 4. Dimensions and Signal Assignments Page 27 of 63 www..com DD 2.X PowerPC 750FX RISC Microprocessor . Preliminary Table 4-2. Signal Locations Signal A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 Ball Location E20 E19 D20 C20 D19 C19 A20 E16 B20 E17 B18 A18 A17 A19 A16 B16 B10 B9 A9 B7 A7 D8 A5 B6 D7 D5 B5 B4 A4 A3 B3 E5 Signal DH0 DH1 DH2 DH3 DH4 DH5 DH6 DH7 DH8 DH9 DH10 DH11 DH12 DH13 DH14 DH15 DH16 DH17 DH18 DH19 DH20 DH21 DH22 DH23 DH24 DH25 DH26 DH27 DH28 DH29 DH30 DH31 Ball Location W18 T17 Y20 Y19 W20 V19 U19 T16 T19 U20 V20 R19 N17 P17 R20 P20 N20 P19 M20 L20 M19 L19 K20 J19 K19 G20 H20 H17 H19 F19 G17 F20 Signal DL0 DL1 DL2 DL3 DL4 DL5 DL6 DL7 DL8 DL9 DL10 DL11 DL12 DL13 DL14 DL15 DL16 DL17 DL18 DL19 DL20 DL21 DL22 DL23 DL24 DL25 DL26 DL27 DL28 DL29 DL30 DL31 Ball Location A2 A1 C2 E4 C1 E2 D2 E1 D1 F1 G2 F2 H2 H4 G1 K2 J2 K1 J1 L2 M2 L1 N2 N4 N1 P1 P4 P2 R2 R1 U2 T1 AACK ABB AGND ARTRY BG BR BVSEL CHECKSTOP (CKSTP_OUT) CI CLK_OUT CKSTP (CKSTP_IN) DBB DBDIS DBG DBWO DRTRY GBL HRESET INT L1_TSTCLK L2_TSTCLK LSSD_MODE MCP PLL_CFG0 PLL_CFG1 PLL_CFG2 PLL_CFG3 PLL_CFG4 PLL_RNG0 PLL_RNG1 QACK QREQ RSRV SMI SRESET SYSCLK Signal Ball Location A8 Y6 Y14 W7 W4 Y3 W9 Y12 T4 T5 Y10 U7 A10 Y5 A6 W3 W1 Y11 Y9 Y13 W13 U13 W12 Y18 W17 Y17 U16 W14 W15 U14 Y8 U8 Y4 W10 Y7 W16 4. Dimensions and Signal Assignments Page 28 of 63 Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 www..com Preliminary DD 2.X PowerPC 750FX RISC Microprocessor Table 4-2. Signal Locations (Continued) Signal Ball Location Signal AP0 AP1 AP2 AP3 Ball Location D16 D13 A13 B8 Signal DP0 DP1 DP2 DP3 DP4 DP5 DP6 DP7 Ball Location T20 N19 J20 G19 B1 G4 H1 M1 TA TBEN TBST TCK TDI TDO TEA TLBISYNC TMS TRST TS TSIZ0 TSIZ1 TSIZ2 TT0 TT1 TT2 TT3 TT4 WT Signal Ball Location A12 W8 A11 T2 V2 W5 W6 W11 V1 U1 B15 A14 B12 B11 D14 B17 B14 A15 B13 U5 Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 4. Dimensions and Signal Assignments Page 29 of 63 www..com DD 2.X PowerPC 750FX RISC Microprocessor Preliminary Table 4-3. Voltage and Ground Assignments A1VDD Y15 A2VDD Y16 OVDD C4 C14 D3 E10 G3 G14 H5 K5 L5 N5 P3 P14 T10 U3 V4 V14 OVDD C7 C17 D18 E11 G7 G18 H16 K16 L16 N16 P7 P18 T11 U18 V7 V17 VDD C10 E8 F6 F12 J8 J13 K8 K13 L3 L11 L18 M9 R6 R12 T8 V10 VDD C11 E13 F9 F15 J9 K3 K11 K18 L8 L13 M8 M13 R9 R15 T13 V11 GND B2 C5 C13 D10 E3 E14 F10 G5 G13 H3 H9 H13 J12 K7 K14 L4 L10 L17 N3 N9 N13 P5 P13 R10 T3 T14 U10 V5 V13 W2 GND B19 C8 C16 D11 E7 E18 F11 G8 G16 H8 H12 H18 K4 K10 K17 L7 L14 M12 N8 N12 N18 P8 P16 R11 T7 T18 U11 V8 V16 W19 4. Dimensions and Signal Assignments Page 30 of 63 Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 www..com Preliminary DD 2.X PowerPC 750FX RISC Microprocessor 5. System Design Information This section provides electrical and thermal design recommendations for successful application of the 750FX. For more information, see the PowerPC FAQ, the PowerPC 750FX Errata list, any applicable PCNs, and the other PowerPC documentation and application notes in the PowerPC Technical Library on our web site. 5.1 PLL Considerations The 750FX design includes two PLLs (PLL0 and PLL1), allowing the processor clock frequency to dynamically change between the PLL frequencies via software control. Use the bits in the HID1 register to specify: 1. The frequency range of each PLL 2. The clock multiplier for each PLL 3. External or internal control of PLL0 4. The selected PLL (which is the source of the processor clock at any given time) For HID1 bit definitions, see the PowerPC 750 FX User's Manual. Note: The PLL configuration must adhere to the supported frequency range as specified in this document and in the IBM 750FX Datasheet Supplement for DD2.X Product Revisions, for the minimum VDD condition. Voltages (VDD/AVDD) should remain constant at all times. At power-on reset, the HID1 register contains zeroes for all the non-read-only bits (bits 7 to 31). This configuration corresponds to the selection of PLL0 as the source of the processor clocks and selects the external configuration and range pins to control PLL0. The external configuration and range pin values are accessible to software using HID1 read-only bits 0-6. PLL1 is always controlled by its internal configuration and range bits. The HID1 setting associated with hard reset corresponds to a PLL1 configuration of clock off, and selection of the medium frequency range. HRESET must be asserted during power up long enough for the PLL(s) to lock, and for the internal hardware to be reset. Once this timing is satisfied, HRESET can be negated. The processor now will proceed to execute instructions, clocked by PLL0 as configured via the external pins. The processor clock frequency can be modified from this initial setting in one of two ways. First, as with earlier designs, HRESET can be asserted, and the external configuration pins can be set to a new value. The machine state is lost in this process, and, as always, HRESET must be held asserted while the PLL relocks, and the internal state is reset. Second, the introduction of another PLL provides an alternative means of changing the processor clock frequency, which does not involve the loss of machine state nor a delay for PLL relock. The following sequence can be used to change processor clock frequency. Note: Assume PLL0 is currently the source for the processor clock. 1. Configure PLL1 to produce the desired clock frequency by setting HID1[PR1] and HID1[PC1] to the appropriate values. 2. Wait for PLL1 to lock. The lock time is the same for both PLLs and is provided in the hardware specification. 3. Set HID1[PS] to 1 to initiate the transition from PLL0 to PLL1 as the source of the processor clocks. From the time the HID1 register is updated to select the new PLL, the transition to the new clock frequency will complete within three (3) bus cycles. After the transition, the HID(PSS) bit indicates which PLL is in use. Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 5. System Design Information Page 31 of 63 www..com DD 2.X PowerPC 750FX RISC Microprocessor Preliminary After both PLLs are running and locked, the processor frequency can be toggled with very low latency. For example, when it is time to change back to the PLL0 frequency, there is no need to wait for PLL lock. HID1[PS] can be reset to 0, causing the processor clock source to transition from PLL1 back to PLL0. If PLL0 will not be needed for some time, it can be configured to be off while not in use. This is done by resetting the HID1[PC0] field to 0, and setting HID1[PI0] to 1. Turning the non-selected PLL off results in a modest power savings, but introduces added latency when changing frequency. If PLL0 is configured to be off, the procedure for switching to PLL0 as the selected PLL involves changing the configuration and range bits, waiting for lock, and then selecting PLL0, as described in the previous paragraph. 5.1.1 Restrictions and Considerations for PLL Configuration Avoid the following when reconfiguring the PLLs: 1. The configuration and range bits in HID1 should only be modified for the non-selected PLL, since it will require time to lock before it can be used as the source for the processor clock. 2. The HID1[PI0] bit should only be modified when PLL0 is not selected. 3. Whenever one of the PLLs is reconfigured, it must not be selected as the active PLL until enough time has elapsed for the PLL to lock. 4. At all times, the frequency of the processor clock, as determined by the various configuration settings, must be within the specification range for the current operating conditions. 5. Never select a PLL that is in the `off' configuration. 5.1.1.1 Configuration Restriction on Frequency Transitions It is considered a programming error to switch from one PLL to the other when both are configured in a half-cycle multiplier mode. For example, with PLL0 configured in 9:2 mode (cfg = 01001) and PLL1 configured in 13:2 mode (cfg = 01101), changing the select bit (HID1[PS]) is not allowed. In cases where such a pairing of configurations is desired, an intermediate full-cycle configuration must be used between the two half-cycle modes. For example, with PLL0 at 9:2, PLL1, configured at 6:1 is selected, then PLL0 is reconfigured at 13:2, locked and selected. 5.1.2 PLL_RNG[0:1] Definitions for Dual PLL Operation The dual PLLs on the 750FX are configured by the PLL_CFG[0:4] and PLL_RNG[0:1] signals. For a given SYSCLK (bus) frequency, the PLL configuration signals set the internal CPU and VCO frequency of operation. The PLL range configuration, for dual PLL operation, for the 750FX is shown in the following table. Table 5-1. PLL_RNG [0:1] Definitions for Dual PLL Operation PLL_RNG[0:1] 00 10 01 11 PLL Frequency Range 600 MHz and above Below 600 MHz Reserved Reserved 5. System Design Information Page 32 of 63 Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 www..com Preliminary DD 2.X PowerPC 750FX RISC Microprocessor 5.1.3 PLL Configuration PLL-CFG (Table 5-2) must be set so that both SYSCLK and the core frequency are within the Clock AC Timing Specifications shown in Table 3-6 on page 13. In addition, the core frequency must not exceed the limit specified in the part number, and the system must meet the required specifications. Table 5-2. 750FX Microprocessor PLL Configuration PLL_CFG [0:4] Processor to Bus Frequency Ratio (PBFR) Binary 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 Notes: 1. The 2X- 2.5X Processor to Bus Ratios are currently not supported. 2. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set for 1:1 mode operation. This mode is intended for factory use only. The AC timing specifications given in the document do not apply in PLL-bypass mode. 3. In Clock-off mode, no clocking occurs inside the 750FX regardless of the SYSCLK input. Decimal 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 OFF OFF PLL Bypass2 PLL Bypass2 2x1 2.5x1 3x 3.5x 4x 4.5x 5x 5.5x 6x 6.5x 7x 7.5x 8x 8.5x 9x 9.5x 10x 11x 12x 13x 14x 15x 16x Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 5. System Design Information Page 33 of 63 www..com DD 2.X PowerPC 750FX RISC Microprocessor Preliminary Table 5-2. 750FX Microprocessor PLL Configuration (Continued) PLL_CFG [0:4] Processor to Bus Frequency Ratio (PBFR) Binary 11011 11100 11101 11110 11111 Notes: 1. The 2X- 2.5X Processor to Bus Ratios are currently not supported. 2. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set for 1:1 mode operation. This mode is intended for factory use only. The AC timing specifications given in the document do not apply in PLL-bypass mode. 3. In Clock-off mode, no clocking occurs inside the 750FX regardless of the SYSCLK input. Decimal 27 28 29 30 31 17x 18x 19x 20x Off3 5. System Design Information Page 34 of 63 Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 www..com Preliminary DD 2.X PowerPC 750FX RISC Microprocessor 5.2 PLL Power Supply Filtering The 750FX microprocessor has two separate AVDD signals (A1VDD and A2VDD) which provide power to the clock generation phase-locked loops. Most designs are expected to utilize a single PLL configuration mode throughout the application. These type of designs should use the default, A1VDD (PLL0) and tie the A2VDD (PLL1) signal to ground (AGND) through a 100 ohm resistor. This is shown in Figure 5-1 on page 36. For designs planning to optimize power savings through dynamic switching between these dual PLL circuits, it is recommended, though not required, that each AVDD have a separate voltage input and filter circuit. To ensure stability of the internal clock, the power supplied to the AVDD input signals should be filtered using a circuit similar to the one shown in Figure 5-1 on page 36. The circuit should be placed as close as possible to the AVDD pin to ensure it filters out as much noise as possible. For descriptions of the sample PLL power supply filtering circuits, see Table 5-3. Table 5-3. Sample PLL Power Supply Filtering Circuits Samples of PLL Power Supply Filtering Circuits Circuit Description Single PLL circuit configuration that uses the A1VDD and ties the A2VDD pin to GND. Single PLL circuit configuration that uses both the A1VDD and the A2VDD pins and a single ferrite bead. Dual PLL configuration that uses a separate circuit for the A1VDD pin and for the A2VDD the pin. Notes: 1. Optional configurations are supported, though not recommended. 2. This circuit design can be used with the Dual PLL feature enabled, though optimum power savings may not be realized. For additional information, see Figure 5-3 Dual PLL Power Supply Filter Circuits on page 38. 3. This circuit design can be used with the Dual PLL feature enabled to optimize power savings. Number of Filtering Circuits 1 1 2 Ferrite Beads 1 1 2 Circuit Figure Recommended Circuit Design Yes Optional Yes 1, 2 2, 3 Notes Figure 5-1 on page 36 Figure 5-2 on page 37 Figure 5-3 on page 38 Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 5. System Design Information Page 35 of 63 www..com DD 2.X PowerPC 750FX RISC Microprocessor Preliminary Figure 5-1. Single PLL Power Supply Filter Circuit with A1VDD Pin and A2VDD Pin Tied to GND Single PLL (A1VDD) Power Supply Filter Circuit (Recommended) Discrete Resistor 2 Ferrite Bead1 A1VDD Pin A2VDD2 Pin AVDD (VDD) C1 C2 Discrete Resistor 100 AGND Pin1 Legend: Item Resistor C1 C2 Ferrite Bead Note: 1. Connected to ground without a filter. 2. Single PLL0 only. Description/Value 2 0.1 F, Ceramic 10.0 F, Ceramic 30 (typical) - Murata BLM21P300S or similar 5. System Design Information Page 36 of 63 Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 www..com Preliminary DD 2.X PowerPC 750FX RISC Microprocessor Figure 5-2. PLL Power Supply Filter Circuit with Two AVDD Pins and One Ferrite Single PLL (A1VDD) Power Supply Filter Circuit (Optional) Discrete Resistor 2 Ferrite Bead1 A1VDD Pin A2VDD Pin AVDD (VDD) C1 C2 AGND Pin1 Legend: Item Resistor C1 C2 Ferrite Bead Note: 1. Connected to ground without a filter. Description/Value 2 0.1 F Ceramic 10.0 F Ceramic 30 (typical) - Murata BLM21P300S or similar Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 5. System Design Information Page 37 of 63 www..com DD 2.X PowerPC 750FX RISC Microprocessor Preliminary Figure 5-3. Dual PLL Power Supply Filter Circuits Dual PLL (AVDD) Power Supply Filter Circuits1 (Recommended configuration if Dual PLL feature is enabled.) Discrete Resistor 2 Ferrite Bead A1VDD Pin AVDD (VDD) C1 C2 AGND Pin 2 Discrete Resistor 2 Ferrite Bead A2VDD Pin AVDD (VDD) C1 C2 AGND Pin 2 Item Resistor C1 C2 Ferrite Bead Notes: Description/Value 2 0.1 F Ceramic 10.0 F Ceramic 30 (typical) - Murata BLM21P300S or similar 1. The dual PLL power supply circuits shown in this figure are recommended for a design that uses the Dual PLL feature. For more information about the Dual PLL feature, see Section 5.2 Low Voltage Operation at Lower Frequency on page 40. 2. Connected to ground without a filter. 5. System Design Information Page 38 of 63 Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 www..com Preliminary DD 2.X PowerPC 750FX RISC Microprocessor 5.3 Decoupling Recommendations Capacitor decoupling is required for the 750FX. Decoupling capacitors act to reduce high frequency chip switching noise and provide localized bulk charge storage to reduce major power surge effects. High frequency decoupling capacitors should be located as close as possible to the processor with low lead inductance to the ground and voltage planes. Decoupling capacitors are recommended on the back of the card, directly opposite the module. The recommended placement and number of decoupling capacitors, 34 VDD-GND caps and 44 OVDD-GND caps are described in Figure 5-4 Orientation and Layout of the 750FX Decoupling Capacitors. The recommended decoupling capacitor specifications are provided in Table 5-4 Recommended Decoupling Capacitor Specifications. The placement and usage described here are guidelines for decoupling capacitors and should be applied for system designs. Table 5-4. Recommended Decoupling Capacitor Specifications Item Description Type X5R or Y5V 10V minimum 0402 size 40 x 20 mils, nominally 1.0 mm x 0.5 mm 0.1 mm on both dimensions 100 nF Recommended minimum number of decoupling capacitors on the back of the card: 34 VDD-GND caps 44 OVDD-GND caps Decoupling capacitor specifications: The decoupling capacitor electrodes are located directly opposite from their corresponding BGA pins where possible. Also, each electrode for each decoupling capacitor needs to be connected to one or more BGA pins (balls) with a short electrical path. Thus, through-vias adjacent to the decoupling capacitors are recommended. The card designer can expand on the decoupling capacitor recommendations by doing the following: * Adding additional decoupling capacitors If using additional decoupling capacitors, verify that these additional capacitors do not reduce the number of card vias or cause the vias to lose proximity to each capacitor electrode. * Adding additional through-vias or blind-vias Card technologies are available that will reduce the inductance between the decoupling capacitor and the BGA pin (ball). Replacing single vias with multiple vias is very effective. Place GND vias close to VDD or OVDD vias to reduce loop inductance. For more information on power layout and bypassing, see the IBM Application Note, "PowerPC 750FX Layout and Bypassing. Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 5. System Design Information Page 39 of 63 www..com DD 2.X PowerPC 750FX RISC Microprocessor Preliminary Figure 5-4. 750FX Pin Locations: OVDD, VDD, GND, and Signal Pins Y W V U T R P N M L K J H G F E D C B A G G O O G O G G O O G V G V O V V G G O O G G O G G O O G V O G G V V V V G G V G O G V G O G V G O G O G V V G V G G V G G V V G G G G G V V G O G O G V G O G V G O G V G G V V V V G G O V G O O G G O G G O O G G V V O V G V G O O G G O G O O G G 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 G = GND Pin V = VDD Pin O = OVDD Pin = Signal Pin Bottom View 5. System Design Information Page 40 of 63 Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 www..com Preliminary DD 2.X PowerPC 750FX RISC Microprocessor Figure 5-5. Orientation and Layout of the 750FX Decoupling Capacitors Y W V U T R P N M L K J H G F E D C B A G G ov O G ov O G vg V V vd G O ov G O ov vg OG vg ov vg G O ov vg vg OG vg vg ov vg V ov ov GV vd vd OG vd vg ov V V G G O G V G O vg vg ov V vd G G V V V V G G G V V G O vg ov G O vg ov O G G vd O vg vd G G vd vg vg V ov ov vg G O ov vg vg ov GV vg vd vg vd G G vd vg G G vd ov O G OG G vg vd G V vd vg G V vg vd V G vg vd vg vg V V vd G O ov G O GO G G GO vg ov O G vg GV GV vd V G G GV GV vg vg vd vg vg G OG OG G ov vg ov ov V vg ov vg vg ov ov V O G vg OG G vd GV vd vg V ov vg G O G V G GO vd V G GV O G V ov vg vg vg ov OG vd GO vg GO ov G 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 G = AGND Pin V = AVDD Pin G = GND Pin V = VDD Pin O = OVDD Pin = Signal Pin vg = GND Via vd = VDD Via ov = OVDD Via = OVDD GND Cap = VDD GND Cap Bottom View Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 5. System Design Information Page 41 of 63 www..com DD 2.X PowerPC 750FX RISC Microprocessor Preliminary 5.4 Output Buffer DC Impedance The 750FX 60x drivers were characterized over various process, voltage, and temperature conditions. To measure Z0, an external resistor is connected to the chip pad, either to OVDD or GND. Then the value of such resistor is varied until the pad voltage is OVDD/2 (see Figure 5-6). The output impedance is actually the average of two resistances: the resistance of the pull-up and the resistance of pull-down devices. When Data is held low, SW1 is closed (SW2 is open), and RN is trimmed until Pad = OVDD/2. RN then becomes the resistance of the pull-down devices. When Data is held high, SW2 is closed (SW1 is open), and RP is trimmed until Pad = OVDD/2. RP then becomes the resistance of the pull-up devices. With a properly designed driver RP and RN are close to each other in value, then Z0 = (RP + RN)/2. Figure 5-6. Driver Impedance Measurement OVDD RP SW2 Pad Data SW1 RN GND 5. System Design Information Page 42 of 63 Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 www..com Preliminary DD 2.X PowerPC 750FX RISC Microprocessor Table 5-5 summarizes the driver impedance characteristics a designer uses to design a typical process. Table 5-5. Driver Impedance Characteristics Process Worst Typical Best Worst Typical Best Worst Typical Best 60x Impedance () 50 44 36 50 44 36 65 50 35 OVDD (V) 1.70 1.80 1.90 238 2.50 2.63 3.14 3.30 3.46 Temperature (C) 105 65 0 105 65 0 105 65 0 5.4.1 Input-Output Usage Table 5-6 Input-Output Usage provides details on the input-output usage of the PowerPC 750FX RISC Microprocessor signals. The Usage Group column refers to the general functional category of the signal. In the PowerPC 750FX RISC Microprocessor, certain input-output signals have pullups and pulldowns, which may or may not be enabled. In Table 5-6, the Input/Output with Internal Resistors column defines which signals have these pullups or pulldowns and their active or inactive state. The Level Protect column defines which signals have the designated function added to their Input/Output cell. For more about Level Protection, see Section 5.5 Level Protection on page 48. Caution: This section is based on preliminary information and is subject to change. Pull L2_TSTCLK and LSSD_MODE high for normal operation. Pins shown as No Connect (NC) must not be connected. Connect all GND pins to ground. Connect all VDD and OVDD pins to the appropriate supply. Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 5. System Design Information Page 43 of 63 www..com Page 44 of 63 5. System Design Information Datasheet DD 2.X PowerPC 750FX RISC Microprocessor Table 5-6. Input-Output Usage 750FX Signal Name A1VDD A2VDD A[0:31] AACK ABB AGND AP[0:3] ARTRY BG BR BVSEL CHECKSTOP CI CKSTP_IN CLK_OUT DBB DBDIS DBG DBWO Active Level -- -- High Low Low -- High Low Low Low N/A Low Low Low High Low Low Low Low Input/ Output -- -- Input/Output Input Input/Output -- Input/Output Input/Output Input Output Input Output Output Input Output Input/Output Input Input Input Data Arbitration Address Termination Address Arbitration Address Arbitration Input/Output Level Interrupt/Resets Transfer Attributes Interrupt/Resets Keeper Keeper Keeper Keeper Keeper Keeper Keeper Keeper Active driver or tie low 5K Pullup required to OVDD Must be actively driven Power Supply Keeper Keeper Keeper Keeper 5K 5K 5K Pullup required to OVDD Active driver or pulldown Chip actively drives Pullup/pulldown, as required Pullup required to OVDD 3, 4 3, 4, 5 3, 4, 5 3, 4, 5 5 3, 4, 5 1, 3, 4 3, 4, 5 3, 4 3, 4, 5 3, 4 3, 4, 5 3, 4 Usage Group Power Supply Power Supply Address Bus Address Termination Keeper Keeper Keeper 5K Must be actively driven Pullup required to OVDD 1, 3, 4 3, 4, 5 3, 4, 5 Input/Output with Internal Pullup Resistors Level Protect Required External Resistor Comments Notes Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 Notes: 1. Depends on the system design. The electrical characteristics of the 750FX do not add additional constraints to the system design, so whatever is done with the net will depend on the system requirements. 2. HRESET, SRESET, and TRST are signals used for ESP and RISCWatch to enable proper operation of the debuggers. Logical AND gates should be placed between these signals and PowerPC 750FX RISC Microprocessor. (Refer to Figure 5-7 on page 48.) 3. The 750FX provides protection from meta-stability on inputs through the use of a "keeper" circuit on specific inputs. Refer to Level Protection on page 48 for a more detailed description. 4. If a system design requires a signal level to be maintained while not being actively driven, an external resistor or device must be used (Keepers assure no meta-stability of inputs but do not guarantee a level). 5. The 750FX does not require external pullups on address and data lines. Control lines must be treated individually. Preliminary www..com Table 5-6. Input-Output Usage (Continued) 750FX Signal Name DH[0:31] DL[0:31] DP[0:7] DRTRY GBL GND HRESET INT L1_TSTCLK L2_TSTCLK LSSD_MODE MCP OVDD PLL_CFG[0:4] PLL_RNG[0:1] QACK QREQ RSRV SMI SRESET Active Level High High High Low Low -- Low Low High High Low Low -- High High Low Low Low Low Low Input/ Output Input/Output Input/Output Input/Output Input Input/Output -- Input Input Input Input Input Input -- Input Input Input Output Output Input Input Interrupt/Resets Control Status/Control Transfer Attributes Power Supply Interrupt/Resets Interrupt/Resets LSSD LSSD LSSD Interrupt/Resets Power Supply Clock Control Keeper Keeper Keeper Keeper Keeper Keeper Keeper Active driver or pullup As required As required Pullup/pulldown, as required Pullup/pulldown, as required Must be actively driven Chip actively drives No connect 3, 4, 5 3, 4, 5 3, 4, 5 3, 4, 5 3, 4, 5 3, 4 2, 3, 4, 5 Not enabled Not enabled Not enabled Keeper Keeper Keeper 5K 5K 5K Active driver Active driver or pullup Pullup/pulldown, as required Pullup required to OVDD Pullup required to OVDD Active driver or pullup 2, 3, 4, 5 3, 4, 5 5 5 5 3, 4, 5 Keeper Keeper 3, 4 1, 3, 4 Usage Group Data Bus Data Bus Input/Output with Internal Pullup Resistors Level Protect Keeper Keeper Required External Resistor Comments Notes 1, 3, 4 1, 3, 4 Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 5. System Design Information Preliminary Datasheet DD 2.X PowerPC 750FX RISC Microprocessor Notes: 1. Depends on the system design. The electrical characteristics of the 750FX do not add additional constraints to the system design, so whatever is done with the net will depend on the system requirements. 2. HRESET, SRESET, and TRST are signals used for ESP and RISCWatch to enable proper operation of the debuggers. Logical AND gates should be placed between these signals and PowerPC 750FX RISC Microprocessor. (Refer to Figure 5-7 on page 48.) 3. The 750FX provides protection from meta-stability on inputs through the use of a "keeper" circuit on specific inputs. Refer to Level Protection on page 48 for a more detailed description. 4. If a system design requires a signal level to be maintained while not being actively driven, an external resistor or device must be used (Keepers assure no meta-stability of inputs but do not guarantee a level). 5. The 750FX does not require external pullups on address and data lines. Control lines must be treated individually. Page 45 of 63 www..com Table 5-6. Input-Output Usage (Continued) 750FX Signal Name SYSCLK TA TBEN TBST TCK Active Level Input/ Output Input Input Input Input/Output Input Transfer Attributes JTAG Not enabled Keeper External pulldown Internal enabled Keeper Keeper Keeper Internal enabled Active driver or pullup Must be actively driven 50a@2.5V 25a@1.8V (the pullup current for the internal resistor) 50a@2.5V 25a@1.8V (the pullup current for the internal resistor) 5K Pullup required to OVDD 5K to GND 50a@2.5V 25a@1.8V (the pullup current for the internal resistor) 1, 3, 4 5 Usage Group Input/Output with Internal Pullup Resistors Level Protect Required External Resistor Comments Notes Page 46 of 63 5. System Design Information Datasheet DD 2.X PowerPC 750FX RISC Microprocessor High Low High Low High Clock Control Data Termination Keeper Keeper No resistor by Active driver design Active driver 3, 4, 5 3, 4, 5 TDI High Input JTAG Enabled high 5 TDO TEA TLBISYNC High Low Low Output Input Input JTAG Data Termination Control 3, 4 3, 4, 5 3, 4 TMS High Input JTAG Enabled high 5 TRST Low Input JTAG Enabled high Internal enabled Keeper Keeper 2, 5 TS TSIZ[0:2] Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 Notes: Low High Input/Output Output Address Start Transfer Attributes 3, 4, 5 1, 3, 4 1. Depends on the system design. The electrical characteristics of the 750FX do not add additional constraints to the system design, so whatever is done with the net will depend on the system requirements. 2. HRESET, SRESET, and TRST are signals used for ESP and RISCWatch to enable proper operation of the debuggers. Logical AND gates should be placed between these signals and PowerPC 750FX RISC Microprocessor. (Refer to Figure 5-7 on page 48.) 3. The 750FX provides protection from meta-stability on inputs through the use of a "keeper" circuit on specific inputs. Refer to Level Protection on page 48 for a more detailed description. 4. If a system design requires a signal level to be maintained while not being actively driven, an external resistor or device must be used (Keepers assure no meta-stability of inputs but do not guarantee a level). 5. The 750FX does not require external pullups on address and data lines. Control lines must be treated individually. Preliminary www..com Table 5-6. Input-Output Usage (Continued) 750FX Signal Name TT[0:4] VDD WT Notes: 1. Depends on the system design. The electrical characteristics of the 750FX do not add additional constraints to the system design, so whatever is done with the net will depend on the system requirements. 2. HRESET, SRESET, and TRST are signals used for ESP and RISCWatch to enable proper operation of the debuggers. Logical AND gates should be placed between these signals and PowerPC 750FX RISC Microprocessor. (Refer to Figure 5-7 on page 48.) 3. The 750FX provides protection from meta-stability on inputs through the use of a "keeper" circuit on specific inputs. Refer to Level Protection on page 48 for a more detailed description. 4. If a system design requires a signal level to be maintained while not being actively driven, an external resistor or device must be used (Keepers assure no meta-stability of inputs but do not guarantee a level). 5. The 750FX does not require external pullups on address and data lines. Control lines must be treated individually. Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 5. System Design Information Preliminary Active Level High -- Low Input/ Output Input/Output -- Output Usage Group Transfer Attributes Power Supply Transfer Attributes Input/Output with Internal Pullup Resistors Level Protect Keeper Required External Resistor Comments Notes 1, 3, 4 Keeper 1, 3, 4 Datasheet DD 2.X PowerPC 750FX RISC Microprocessor Page 47 of 63 www..com DD 2.X PowerPC 750FX RISC Microprocessor Preliminary Figure 5-7. IBM RISCWatchTM JTAG to HRESET, TRST, and SRESET Signal Connector HRESET from RISCWatch HRESET to PowerPC 750FX System HRESET TRST to PowerPC 750FX TRST from RISCWatch SRESET from RISCWatch System SRESET Note: See notes for Table 5-6 Input-Output Usage on page 44. SRESET to PowerPC 750FX 5.5 Level Protection A level protection feature is included in the PowerPC 750FX RISC Microprocessor. The level protection feature is available in the 1.8V, 2.5V, and 3.3V bus modes. This feature prevents ambiguous floating reference voltages by pulling the respective signal line to the last valid or nearest valid state. For example, if the Input/Output voltage level is closer to OVDD, the circuit pulls the I/O level to OVDD. If the I/O level is closer to GND, the I/O level is pulled low. This self-latching circuitry keeps the floating inputs defined and avoids meta-stability. In Table 5-6 Input-Output Usage on page 44, these signals are defined as keeper in the Level Protect column. Keepers are not intended to force a net to a particular state. The keeper supplies a small (100 A max.) amount of current, which is intended to help keep a net at the current logic state. The level protect circuitry provides no additional leakage current to the signal I/O; however, some amount of current must be applied to the keeper node to overcome the level protection latch. This current is process dependent, but in no case is the current required over 100A. This feature allows the system designer to limit the number of resistors in the design and optimize placement and reduce costs. Note: Having a level protection (keeper) on the associated signal I/O does not replace a pull-up or pull-down resistor that is needed by the 750FX or a separate device located on the 60x bus. The designer must supply any such resisters. 5. System Design Information Page 48 of 63 Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 www..com Preliminary DD 2.X PowerPC 750FX RISC Microprocessor 5.6 64 or 32-Bit Data Bus Mode This mode selection varies for different design revision (DD) levels. For the 750FX DD2.X, mode setting is determined by the state of the mode signal, TLBISYNC, at the transition of HRESET from low to high. If TLBISYNC is high when HRESET transitions from active to inactive, 64-bit mode is selected. If TLBISYNC is low when HRESET transitions from active to inactive, 32-bit mode is selected. Special Note: (Reduced pin out mode) To transition from a previous processor with reduced pin out mode, drive TLBISYNC appropriately, leave the DP(0..7) and AP(0..3) pins floating, and disable parity checking. The 750FX does not have APE and DPE pins. 5.7 IIO Voltage Mode Selection Selection between 1.8V, 2.5V, or 3.3V I/O modes is accomplished by using the BVSEL and L1_TSTCLK pins: * If BVSEL = 1 and L1_TSTCLK = 0, then the 3.3V mode is enabled. * If BVSEL = 1 and L1_TSTCLK = 1, then the 2.5V mode is enabled. * If BVSEL = 0 and L1_TSTCLK = 1, then the 1.8V mode is enabled. Note: Do not set BVSEL = 0 and L1_TSTCLK = 0 since it yields an INVALID MODE. Table 5-7. Summary of Mode Select Mode 32-bit mode Sample TLBISYNC to select HIGH = 64-bit mode LOW = 32-bit mode 3.3V +/- 165mV (BVSEL = 1, L1_TSTCLK = 0) or 2.5V +/- 125mV (BVSEL = 1, L1_TSTCLK = 1) or 1.8V +/- 100mV (BVSEL = 0, L1_TSTCLK = 1) 750FX (DD2.x) I/O mode selection 5.8 Thermal Management This section provides thermal management information for the CBGA package for air cooled applications. Proper thermal control design is primarily dependent upon the system-level design; that is, the heat sink, air flow, and the thermal interface material. To reduce the die-junction temperature, heat sinks may be attached to the package by several methods: adhesive, spring clip to holes in the printed-circuit board or package, mounting clip, or a screw assembly, see Figure 5-10 Package Exploded Cross-Sectional View with Several Heat Sink Options on page 54. In general, a heat sink is required for all 750FX applications. A design example is included in this section. 5.8.1 Heat Sink Selection Example For preliminary heat sink sizing, the die-junction temperature can be expressed as follows: Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 5. System Design Information Page 49 of 63 www..com DD 2.X PowerPC 750FX RISC Microprocessor Preliminary TJ = TA + TR + (JC + INT + SA) x PD Where: TJ is the die-junction temperature TA is the inlet cabinet ambient temperature TR is the air temperature rise within the system cabinet JC is the junction-to-case thermal resistance INT is the thermal resistance of the thermal interface material SA is the heat sink-to-ambient thermal resistance PD is the power dissipated by the device Typical die-junction temperatures (TJ) should be maintained less than the value specified in Table 3-3 Package Thermal Characteristics1 on page 10. The temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air temperature rise within the computer cabinet. An electronic cabinet inlet-air temperature (TA) may range from 30 to 40C. The air temperature rise within a cabinet (TR) may be in the range of 5 to 10C. The thermal resistance of the interface material (INT) is typically about 1C/W. Assuming a TA of 30C, a TR of 5C, a CBGA package JC = 0.03, and a power dissipation (PD) of 5.0 watts, the following expression for TJ is obtained. Die-junction temperature: TJ = 30C + 5C + (0.03C/W +1.0C/W + SA) x 5W For a Thermalloy heat sink #2328B, the heat sink-to-ambient thermal resistance (SA) versus air flow velocity is shown in Figure 5-8 Thermalloy #2328B Pin-Fin Heat Sink-to-Ambient Thermal Resistance vs. Airflow Velocity on page 51. 5. System Design Information Page 50 of 63 Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 www..com Preliminary DD 2.X PowerPC 750FX RISC Microprocessor Figure 5-8. Thermalloy #2328B Pin-Fin Heat Sink-to-Ambient Thermal Resistance vs. Airflow Velocity Thermalloy #2328B Pin-fin Heat Sink (25 x 28 x 15 mm) 8 Heat Sink Thermal Resistance (xC/W) 7 6 5 4 3 2 1 0 0.5 1 1.5 2 2.5 3 3.5 Approach Air Velocity (m/s) Assuming an air velocity of 0.5m/s, we have an effective SA of 7C/W, thus TJ = 30C + 5C + (2.2C/W +1.0C/W + 7C/W) x 4.5W, resulting in a junction temperature of approximately 81C which is well within the maximum operating temperature of the component. Other heat sinks offered by Chip Coolers, IERC, Thermalloy, Aavid, and Wakefield Engineering offer different heat sink-to-ambient thermal resistances, and may or may not need air flow. Though the junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure-of-merit used for comparing the thermal performance of various microelectronic packaging technologies, one should exercise caution when only using this metric in determining thermal management because no single parameter can adequately describe three-dimensional heat flow. The final chip-junction operating temperature is not only a function of the component-level thermal resistance, but the system-level design and its operating conditions. In addition to the component's power dissipation, a number of factors affect the final operating die-junction temperature. These factors might include air flow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink attach, next-level interconnect technology, system air temperature rise, and so forth. Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 5. System Design Information Page 51 of 63 www..com DD 2.X PowerPC 750FX RISC Microprocessor Preliminary 5.8.2 Internal Package Conduction For the exposed-die packaging technology, shown in Table 3-3 Package Thermal Characteristics1 on page 10, the intrinsic conduction thermal resistance paths are as follows. * Die junction-to-case thermal resistance (Primary thermal path) * Die junction-to-lead thermal resistance (Not normally a significant thermal path) * Die junction-to-ambient thermal resistance (Largely dependent on customer-supplied heatsink) Figure 5-9 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit board. Figure 5-9. C4 Package with Heat Sink Mounted to a Printed-Circuit Board External Resistance Radiation Convection Heat Sink Thermal Interface Material Die/Package Internal Resistance Chip Junction Package/Leads Printed-Circuit Board External Resistance Radiation Convection (Note the internal versus external package resistance.) Heat generated on the active side (ball) of the chip is conducted through the silicon, then through the heat sink attach material (or thermal interface material), and finally to the heat sink; where it is removed by forcedair convection. Since the silicon thermal resistance is quite small, for a first-order analysis, the temperature drop in the silicon may be neglected. Thus, the heat sink attach material and the heat sink conduction/convective thermal resistances are the dominant terms. The heat flow path from the die, through the chip-to-substrate balls, through the substrate, through the substrate-to-board balls, and through the board to ambient is usually too high of a resistance to offer much cooling. In addition, various factors make the heat flow through this path very difficult to accurately determine. Designers must not depend on cooling the 750FX using this means unless thermal modeling has been confidently completed. 5. System Design Information Page 52 of 63 Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 www..com Preliminary DD 2.X PowerPC 750FX RISC Microprocessor 5.8.3 Minimum Heat Sink Requirements The worst-case power dissipation (PD) for the 750FX is shown in Table 3-5. A conservative thermal management design will provide sufficient cooling to maintain the junction temperature (TJ) of the 750FX below 105C at maximum PD and worst-case ambient temperature and airflow conditions. Many factors affect the 750FX power dissipation, including VDD, TJ, core frequency, process factors, and the code that is running on the processor. In general, PD increases with increases in TJ, VDD, Fcore, process variables, and the number of instructions executed per second. For various reasons, a designer may determine that the power dissipation of the 750FX in their application will be less than the maximum value shown in the Datasheet. Assuming a lower PD will result in a thermal management system with less cooling capacity than would be required for the maximum Datasheet PD. In this case, the designer may decide to determine the actual maximum 750FX PD in the particular application. Contact your IBM PowerPC FAE for more information. In addition to the system factors that must be considered in a cooling system analysis, three things should be noted. First, 750FX PD rises as TJ increases, so it is most useful to measure PD while the 750FX junction temperature is at maximum. While not specified or guaranteed, this rise in PD with TJ is typically less than 1W per 10C. So regardless of other factors, the minimum cooling solution must have a maximum temperature rise of no more than 10C/W. This minimum cooling solution is not generally achievable without a heat sink. A heat sink or heat spreader of some sort must always be used in 750FX applications. Second, due to process variations, there can be a significant variation in the PD of individual 750FX devices. In addition, IBM will occasionally supply "downbinned" parts. These are faster parts that are shipped in lieu of the speed that was ordered. For example, some parts that are marked as 600MHz may actually run as fast as 700MHz. These 700MHz parts will dissipate more power at 600MHz than the 600MHz parts. So power dissipation analysis should be conducted using the fastest parts available. Finally, regardless of methodology, IBM only supports system designs that successfully maintain the maximum junction temperature within Datasheet limits. IBM also supports designs that rely on the maximum PD values given in this Datasheet, and supply a cooling solution sufficient to dissipate that amount of power while keeping the maximum junction temperature below the maximum TJ. Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 5. System Design Information Page 53 of 63 www..com DD 2.X PowerPC 750FX RISC Microprocessor Preliminary 5.8.4 Heat Sink Mounting Figure 5-10. Package Exploded Cross-Sectional View with Several Heat Sink Options Heat Sink CBGA Package Heat Sink clip Adhesive or Thermal Interface Material Printed Circuit Board Option Table 5-8. Maximum Heatsink Weight Limit for the CBGA Force Maximum dynamic compressive force allowed on the BGA balls Maximum dynamic tensile force allowed on the BGA balls Maximum dynamic compressive force allowed on the chip Maximum mass of module + heatsink when heatsink is not bolted to card Maximum 42.9 N 9.05 N 14.8 N 50g 5.8.5 Thermal Assist Unit The thermal sensor in the Thermal Assist Unit (TAU) has not been characterized to determine the basic uncalibrated accuracy. The relationship between the actual junction temperature and the temperature indicated by THRM1 and THRM2 is not well known. IBM recommends that the TAU in these devices be calibrated before use. Calibration methods are discussed in the IBM Application Note Calibrating the Thermal Assist Unit in the IBM25PPC750L Processors. Although this note was written for the 750L, the calibration methods discussed in this document also apply to the 750FX. In rare cases, the basic error of the TAU may be so large that a useful calibration cannot be achieved. 5. System Design Information Page 54 of 63 Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 www..com Preliminary DD 2.X PowerPC 750FX RISC Microprocessor 5.8.6 Adhesives and Thermal Interface Materials A thermal interface material is recommended at the package die-to-heat sink interface to minimize the thermal contact resistance. For those applications where the heat sink is attached by a spring clip mechanism, Figure 5-11 shows the thermal performance of three thin-sheet thermal-interface materials (silicon, graphite/oil, floroether oil), a bare joint, and a joint with thermal grease, as a function of contact pressure. As shown, the performance of these thermal interface materials improves with increasing contact pressure. The use of thermal grease significantly reduces the interface thermal resistance. That is, the bare joint results in a thermal resistance approximately seven times greater than the thermal grease joint. In this example, the heat sink is attached to the package by means of a spring clip to holes in the printedcircuit board (see Figure 5-10 Package Exploded Cross-Sectional View with Several Heat Sink Options on page 54). The synthetic grease offers the best thermal performance, considering the low interface pressure. The selection of any thermal interface material depends on many factors - thermal performance requirements, manufacturability, service temperature, dielectric properties, cost, and so forth. Figure 5-11. Thermal Performance of Select Thermal Interface Material 2 + + Specific Thermal Resistance (Kin2/W) 1.5 + 1 0.5 0 0 10 20 30 40 50 60 70 80 Contact Pressure (PSI) + Silicone Sheet (0.006 inch) Bare Joint Floroether Oil Sheet (0.007 inch) Graphite/Oil Sheet (0.005 inch) Synthetic Grease Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 5. System Design Information Page 55 of 63 www..com DD 2.X PowerPC 750FX RISC Microprocessor Preliminary 5.8.7 Thermal Interface and Adhesive Vendors The board designer can choose between several types of thermal interfaces. Heat sink adhesive materials should be selected based upon high conductivity, yet adequate mechanical strength to meet equipment shock/vibration requirements. A partial list of vendors that advertise thermal interface materials for PowerPC devices is shown in Table 5-9 on page 56. Table 5-9. 750FX Thermal Interface and Adhesive Materials Vendors Company Names and Addresses for Thermal Interfaces and Adhesive Materials Vendors Dow-Corning Corporation Dow-Corning Electronic Materials P.O. Box 0997 Midland, MI 48686-0997 (989) 496-4000 http://www.dowcorning.com/content/etronics Chomerics, Inc. 77 Dragon Court Woburn, MA 01888-4850 (781) 935-4850 http://www.chomerics.com Thermagon, Inc. 4797 Detroit Avenue Cleveland, OH 44102-2216 (216) 939-2300 / (888) 246-9050 http://www.Thermagon.com Loctite Corporation 1001 Trout Brook Crossing Rocky Hill, CT 06067 (860) 571-5100 / (800) 562-8483 http://www.loctite.com AI Technology 70 Washington Road Princeton, NJ 08550-1097 (609) 799-9388 http://www.aitechnology.com 5. System Design Information Page 56 of 63 Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 www..com Preliminary DD 2.X PowerPC 750FX RISC Microprocessor 5.8.8 Heat Sink Vendors The board designer can choose between several types of heat sinks to place on the 750FX. A partial list of vendors that advertise heat sinks for Power PC devices is shown in Table 5-10 A Partial Listing of 750FX Heat Sink Vendors on page 57. Table 5-10. A Partial Listing of 750FX Heat Sink Vendors Company Names and Addresses for Heat Sink Vendors Chip Coolers, Inc. 333 Strawberry Field Rd. Warwick, RI 02886 (800) 227-0254 http://www.chipcoolers.com International Electronic Research Corporation (IERC) 413 North Moss Street Burbank, CA 91502 (818) 842-7277 http://www.ctscorp.com/ierc Aavid Thermalloy 80 Commercial Street Concord, NH 03301 (603) 224-9888 http://www.aavid.com http://www.aavidthermalloy.com Wakefield Thermal Solutions Inc. 33 Bridge Street Pellham, NH 03076 (603) 635-2800 http://www.wakefield.com Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 5. System Design Information Page 57 of 63 www..com DD 2.X PowerPC 750FX RISC Microprocessor Preliminary 5. System Design Information Page 58 of 63 Body_750FX_DS_DD2.X.fm.2.0 June 9, 2003 www..com Preliminary DD2.X PowerPC 750FX RISC Microprocessor Revision Log Date Feb 13, 2003 May 16, 2003 May 23, 2003 June 3, 2003 June 5, 2003 June 6, 2003 June 9, 2003 Description Version 0.1 Initial preliminary version for general release of 750FX DD2.3. Version 1.0 Second preliminary version which includes input/updates from designers. Version 2.0 Third preliminary version which includes input/updates from designers. Version 2.0 Fourth preliminary version which includes input/updates from designers. Version 2.0 Changed from DD2.3 to DD2.X. Also included designer updates. Version 2.0 Changed Table 3-5 Power Consumption. Version 2.0 Removed Rev bars.. Rev_Log_750FX_DS_DD2.X.fm.2.0 June 9, 2003 Revision Log Page 59 of 59 www..com |
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